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? 1. general description the adc1412d is a dual channel 14-bit analog- to-digital converter (adc) optimized for high dynamic performance and low power consumption at sample rates up to 125 msps. pipelined architecture and output error correction ensure the adc1412d is accurate enough to guarantee zero missing codes over t he entire operating range. supplied from a single 3 v source, it can handle output logic levels from 1.8 v to 3.3 v in complementary metal oxide semiconductor (cmos) mode becaus e of a separate digital output supply. it supports the low voltage diffe rential signalling (lvds) doub le data rate (ddr) output standard. an integrated serial peripheral interface (spi) allows the user to easily configure the adc. the device also includes an programmable full-scale spi to allow a flexible input voltage range of 1 v (p-p) to 2 v (p-p). with excellent dynamic performance from the baseband to input frequencies of 170 mhz or more, the adc1412d is ideal for use in communications, imaging and medical applications. 2. features and benefits 3. applications adc1412d series dual 14-bit adc; 65 msps, 80 ms ps, 105 msps or 125 msps; cmos or lvds ddr digital outputs rev. 05 ? 2 july 2012 product data sheet ? snr, 72.1 dbfs ? input bandwidth, 600 mhz ? sfdr, 86 dbc ? power dissipation, 855 mw at 80 msps ? sample rate up to 125 msps ? serial peripheral interface (spi) ? clock input divided by 2 to reduce jitter contribution ? duty cycle stabilizer ? single 3 v supply ? fast out-of-range (otr) detection ? flexible input voltage range: 1vto2v(p-p) ? offset binary, two?s complement, gray code ? cmos or lvds ddr digital outputs ? power-down and sleep modes ? pin and software compatible with adc1212d series and adc1112d125 ? hvqfn64 package ? wireless and wired broadband communications ? portable instrumentation ? spectral analysis ? imaging systems ? ultrasound equipment ? software defined radio
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 2 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 4. ordering information 5. block diagram table 1. ordering information type number f s (msps) package name description version adc1412d125hn-c1 125 hvqfn64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 ? 9 ? 0.85 mm sot804-3 ADC1412D105HN-C1 105 hvqfn64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 ? 9 ? 0.85 mm sot804-3 adc1412d080hn-c1 80 hvqfn64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 ? 9 ? 0.85 mm sot804-3 adc1412d065hn-c1 65 hvqfn64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 ? 9 ? 0.85 mm sot804-3 fig 1. block diagram adc1412d spi interface output drivers output drivers system reference and power management error correction and digital processing adc core 14-bit pipelined t/h input stage inap cs sdio/ods sclk/dfs otra otrb ctrl refat refab refbb refbt cmos: da13 to da0 or lvds/ddr: da12_da13_p to da0_da1_p, da12_da13_m to da0_da1_m cmos: db13 to db0 or lvds/ddr: db12_db13_p to db0_db1_p db12_db13_m to db0_db1_m inam clkp clkm clock input stage and duty cycle control vcma vref sense vcmb 005aaa096 output drivers adc core 14-bit pipelined t/h input stage inbp inbm error correction and digital processing cmos: dav or lvds/ddr: davp davm
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 3 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 6. pinning information 6.1 cmos outputs selected 6.1.1 pinning 6.1.2 pin description fig 2. pin configuration with cmos digital outputs selected 005aaa097 adc1412d hvqfn64 transparent top view db7 inbm inbp db6 agnd db5 vcmb db4 refbt db3 refbb db2 agnd db1 clkm db0 clkp n.c. agnd dav refab da0 refat da1 vcma da2 agnd da3 inam da4 inap da5 vdda vdda sclk/dfs sdio/ods cs ctrl decb otrb db13 db12 db11 db10 db9 db8 vddo vddo vdda vref sense vdda deca otra da13 da12 da11 da10 da9 da8 da7 da6 vddo vddo 16 33 15 34 14 35 13 36 12 37 11 38 10 39 9 40 8 41 7 42 6 43 5 44 4 45 3 46 2 47 1 48 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 terminal 1 index area table 2. pin description (cmos digital outputs) symbol pin type [1] description inap 1 i analog input; channel a inam 2 i complementary analog input; channel a agnd 3 g analog ground vcma 4 o common-mode output voltage; channel a refat 5 o top reference; channel a refab 6 o bottom reference; channel a agnd 7 g analog ground clkp 8 i clock input clkm 9 i complementary clock input agnd 10 g analog ground refbb 11 o bottom reference; channel b refbt 12 o top reference; channel b
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 4 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs vcmb 13 o common-mode output voltage; channel b agnd 14 g analog ground inbm 15 i complementary analog input; channel b inbp 16 i analog input; channel b vdda 17 p analog power supply vdda 18 p analog power supply sclk/dfs 19 i spi clo ck/data format select sdio/ods 20 i/o spi data input/output/output data standard cs 21 i spi chip select, active low ctrl 22 i control mode select decb 23 o regulator decoupling node; channel b otrb 24 o out of range; channel b db13 25 o data output bit 13 (most significant bit (msb)); channel b db12 26 o data output bit 12; channel b db11 27 o data output bit 11; channel b db10 28 o data output bit 10; channel b db9 29 o data output bit 9; channel b db8 30 o data output bit 8; channel b vddo 31 p output power supply vddo 32 p output power supply db7 33 o data output bit 7; channel b db6 34 o data output bit 6; channel b db5 35 o data output bit 5; channel b db4 36 o data output bit 4; channel b db3 37 o data output bit 3; channel b db2 38 o data output bit 2; channel b db1 39 o data output bit 1; channel b db0 40 o data output bit 0 (least significant bit (lsb)); channel b n.c. 41 - not connected dav 42 o data valid output clock da0 43 o data output bit 0 (lsb); channel a da1 44 o data output bit 1; channel a da2 45 o data output bit 2; channel a da3 46 o data output bit 3; channel a da4 47 o data output bit 4; channel a da5 48 o data output bit 5; channel a vddo 49 p output power supply vddo 50 p output power supply da6 51 o data output bit 6; channel a da7 52 o data output bit 7; channel a da8 53 o data output bit 8; channel a da9 54 o data output bit 9; channel a da10 55 o data output bit 10; channel a da11 56 o data output bit 11; channel a table 2. pin description (cmos digital outputs) ?continued symbol pin type [1] description
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 5 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs [1] p: power supply; g: ground; i: input; o: output; i/o: input/output. 6.2 lvds ddr outputs selected 6.2.1 pinning da12 57 o data output bit 12; channel a da13 58 o data output bit 13 (msb); channel a otra 59 o out-of-range; channel a deca 60 o regulator decoupling node; channel a vdda 61 p analog power supply sense 62 i reference programming pin vref 63 i/o voltage reference input/output vdda 64 p analog power supply table 2. pin description (cmos digital outputs) ?continued symbol pin type [1] description fig 3. pin configuratio n with lvds ddr digital outputs selected 005aaa098 adc1412d hvqfn64 transparent top view db6_db7_m inbm inbp db6_db7_p agnd db4_db5_m vcmb db4_db5_p refbt db2_db3_m refbb db2_db3_p agnd db0_db1_m clkm db0_db1_p clkp davm agnd davp refab da0_da1_p refat da0_da1_ m vcma da2_da3_p agnd da2_da3_m inam da4_da5_p inap da4_da5_m vdda vdda sclk/dfs sdio/ods cs ctrl decb otrb db12_db13_m db12_db13_p db10_db11_m db10_db11_p db8_db9_m db8_db9_p vddo vddo vdda vref sense vdda deca otra da12_da13_m da12_da13_p da10_da11_m da10_da11_p da8_da9_m da8_da9_p da6_da7_m da6_da7_p vddo vddo 16 33 15 34 14 35 13 36 12 37 11 38 10 39 9 40 8 41 7 42 6 43 5 44 4 45 3 46 2 47 1 48 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 terminal 1 index area
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 6 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 6.2.2 pin description [1] pins 1 to 24, pin 59 to 64 and pins 31, 32, 49 and 50 are the same for both cmos and lvds ddr outputs (see table 2). [2] p: power supply; g: ground; i: input; o: output; i/o: input/output. table 3. pin description (lvds ddr) digital outputs) [1] symbol pin type [2] description db12_db13_m 25 o differential output data db12 and db13 multiplexed, complement db12_db13_p 26 o differential output data db12 and db13 multiplexed, true db10_db11_m 27 o differential output data db10 and db11 multiplexed, complement db10_db11_p 28 o differential output data db10 and db11 multiplexed, true db8_db9_m 29 o differential output data db8 and db9 multiplexed, complement db8_db9_p 30 o differential output da ta db8 and db9 multiplexed, true db6_db7_m 33 o differential output data db6 and db7 multiplexed, complement db6_db7_p 34 o differential output da ta db6 and db7 multiplexed, true db4_db5_m 35 o differential output data db4 and db5 multiplexed, complement db4_db5_p 36 o differential output da ta db4 and db5 multiplexed, true db2_db3_m 37 o differential output data db2 and db3 multiplexed, complement db2_db3_p 38 o differential output da ta db2 and db3 multiplexed, true db0_db1_m 39 o differential output data db0 and db1 multiplexed, complement db0_db1_p 40 o differential output da ta db0 and db1 multiplexed, true davm 41 o data valid output clock, complement davp 42 o data valid output clock, true da0_da1_p 43 o differential output da ta da0 and da1 multiplexed, true da0_da1_m 44 o differential output data da0 and da1 multiplexed, complement da2_da3_p 45 o differential output da ta da2 and da3 multiplexed, true da2_da3_m 46 o differential output data da2 and da3 multiplexed, complement da4_da5_p 47 o differential output da ta da4 and da5 multiplexed, true da4_da5_m 48 o differential output data da4 and da5 multiplexed, complement da6_da7_p 51 o differential output da ta da6 and da7 multiplexed, true da6_da7_m 52 o differential output data da6 and da7 multiplexed, complement da8_da9_p 53 o differential output da ta da8 and da9 multiplexed, true da8_da9_m 54 o differential output data da8 and da9 multiplexed, complement da10_da11_p 55 o differential output data da10 and da11 multiplexed, true da10_da11_m 56 o differential output data da10 and da11 multiplexed, complement da12_da13_p 57 o differential output data da12 and da13 multiplexed, true da12_da13_m 58 o differential output data da12 and da13 multiplexed, complement
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 7 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 7. limiting values 8. thermal characteristics [1] value for six layers board in still ai r with a minimum of 64 thermal vias. 9. static characteristics table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v o output voltage pins da13 to da0 and db13 to db0 or pins da12_da13_p to da0_da1_p, da12_da13_m to da0_da1_m, db12_db13_p to db0_db1_p and db12_db13_m to db0_db1_m ? 0.4 +3.9 v v dda analog supply voltage ? 0.4 +3.9 v v ddo output supply voltage ? 0.4 +3.9 v t stg storage temperature ? 55 +125 ? c t amb ambient temperature ? 40 +85 ? c t j junction temperature - 125 ? c table 5. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient [1] 15.6 k/w r th(j-c) thermal resistance from junction to case [1] 6.3 k/w table 6. static characteristics [1] symbol parameter conditions min typ max unit supplies v dda analog supply voltage 2.85 3.0 3.4 v v ddo output supply voltage cmos mode 1.65 1.8 3.6 v lvds ddr mode 2.85 3.0 3.6 v i dda analog supply current f clk =125msps; f i =70mhz - 400 - ma i ddo output supply current cmos mode; f clk =125msps; f i =70mhz -18-ma lvds ddr mode: f clk =125msps; f i =70mhz -92-ma
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 8 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs p power dissipation adc1412d125; analog supply only -1230-mw adc1412d105; analog supply only -1130-mw adc1412d080; analog supply only -855-mw adc1412d065; analog supply only - 780 - mw power-down mode - 24 - mw sleep mode - 80 - mw clock inputs: pins clkp and clkm lvpecl v i(clk)dif differential clock input voltage peak-to-peak - ? 1.6 - v sine v i(clk)dif differential clock input voltage peak-to-peak ? 0.8 ? 3.0 - v lvcmos v il low-level input voltage - - 0.3v dda v v ih high-level input voltage 0.7v dda --v logic input: pin ctrl v il low-level input voltage - 0 - v low-medium level - 0.3v dda -v medium-high level - 0.6v dda -v v ih high-level input voltage - v dda -v i il low-level input current ? 10 - +10 ? a i ih high-level input current ? 10 - +10 ? a serial peripheral interface: pins cs , sdio/ods, sclk/dfs v il low-level input voltage 0 - 0.3v dda v v ih high-level input voltage 0.7v dda -v dda v i il low-level input current ? 10 - +10 ? a i ih high-level input current ? 50 - +50 ? a c i input capacitance - 4 - pf digital outputs, cmos mode: pins da13 to da0, db13 to db0, otra, otrb and dav output levels, v ddo =3v v ol low-level output voltage agnd - 0.2v ddo v v oh high-level output voltage 0.8v ddo -v ddo v c o output capacitance high impedance; see table 10 - 3 - pf output levels, v ddo =1.8v v ol low-level output voltage agnd - 0.2v ddo v v oh high-level output voltage 0.8v ddo -v ddo v table 6. static characteristics [1] ?continued symbol parameter conditions min typ max unit
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 9 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs [1] typical values measured at v dda =3v, v ddo =1.8v, t amb =25 ? c; minimum and maximum values are across the full temperature range t amb = ? 40 ? c to +85 ? c at v dda =3v, v ddo = 1.8 v; v inap ? v inam = ? 1 dbfs; v inbp ? v inbm = ? 1 dbfs; internal reference mode; applied to cmos and lvds inte rface; unless otherwise specified. digital outputs, lvds ddr mode: pins da12_da13_p to da0_da1_p, da12_da13_m to da0_da1_m, db12_db13_p to db0_db1_p, db12_db13_m to db0_db1_m, davp and davm output levels, v ddo = 3 v only, r l = 100 ? v o(offset) output offset voltage outpu t buffer current set to 3.5 ma -1.2-v v o(dif) differential output voltage output buffer current set to 3.5 ma -350-mv c o output capacitance - 3 - pf analog inputs: pins i nap, inam, inbp and inbm i i input current ? 5- +5 ? a r i input resistance - 19.8 - k ? c i input capacitance - 2.8 - pf v i(cm) common-mode input voltage v inap =v inam ; v inbp =v inbm 0.9 1.5 2 v b i input bandwidth - 600 - mhz v i(dif) differential input voltage peak-to-peak 1 - 2 v common-mode output voltage: pins vcma and vcmb v o(cm) common-mode output voltage - 0.5v dda -v i o(cm) common-mode output current - 4 - ? a i/o reference voltage: pin vref v vref voltage on pin vref output - 0.5 to 1 - v input 0.5 - 1 v accuracy inl integral non-linearity ? 5 ? 1+5lsb dnl differential non-linearity guaranteed no missing codes ? 0.95 ? 0.5 +0.95 lsb e offset offset error - ? 2-mv e g gain error full-scale - ? 0.5 - % m g(ctc) channel-to-channel gain matching -1.1-% supply psrr power supply rejection ratio 200 mv (p-p) on pin vdda; f i =dc - ? 37 - db table 6. static characteristics [1] ?continued symbol parameter conditions min typ max unit
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 10 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 10. dynamic characteristics 10.1 dynamic characteristics table 7. dynamic characteristics [1] symbol parameter conditions adc1412d065 adc1412d080 adc1412d105 adc1412d125 unit min typ max min typ max min typ max min typ max analog signal processing ? 2h second harmonic level f i = 3 mhz - 87 - - 87 - - 86 - - 88 - dbc f i =30mhz -86- -86- -86- -87-dbc f i =70mhz -85- -85- -84- -85-dbc f i = 170 mhz - 82 - - 82 - - 81 - - 83 - dbc ? 3h third harmonic level f i = 3 mhz - 86 - - 86 - - 85 - - 87 - dbc f i =30mhz -85- -85- -85- -86-dbc f i =70mhz -84- -84- -83- -84-dbc f i = 170 mhz - 81 - - 81 - - 80 - - 82 - dbc thd total harmonic distortion f i = 3 mhz - 83 - - 83 - - 82 - - 84 - dbc f i =30mhz -82- -82- -82- -83-dbc f i =70mhz -81- -81- -80- -81-dbc f i = 170 mhz - 78 - - 78 - - 77 - - 79 - dbc enob effective number of bits f i = 3 mhz - 11.7 - - 11.7 - - 11.6 - - 11.6 - bit f i = 30 mhz - 11.6 - - 11.5 - - 11.5 - - 11.5 - bit f i = 70 mhz - 11.5 - - 11.5 - - 11.4 - - 11.4 - bit f i = 170 mhz - 11.4 - - 11.4 - - 11.3 - - 11.3 - bit snr signal-to-noise ratio f i = 3 mhz - 72.1 - - 72.0 - - 71.8 - - 71.4 - dbfs f i = 30 mhz - 71.3 - - 71.2 - - 71.2 - - 71.1 - dbfs f i = 70 mhz - 70.7 - - 70.7 - - 70.6 - - 70.5 - dbfs f i = 170 mhz - 70.2 - - 70.1 - - 70.0 - - 69.9 - dbfs sfdr spurious-free dynamic range f i = 3 mhz - 86 - - 86 - - 85 - - 87 - dbc f i =30mhz -85- -85- -85- -86-dbc f i =70mhz -84- -84- -83- -84-dbc f i = 170 mhz - 81 - - 81 - - 80 - - 82 - dbc
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 11 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs [1] typical values measured at v dda =3v, v ddo =1.8v, t amb =25 ? c; minimum and maximum values are ac ross the full temperature range t amb = ? 40 ? cto+85 ? c at v dda =3v, v ddo = 1.8 v; v inap ? v inam = ? 1 dbfs; v inbp ? v inbm = ? 1 dbfs; internal reference mode; applied to cmos and lvds interface; unless otherwise specified. 10.2 clock and digital output timing imd intermodulation distortion f i = 3 mhz - 89 - - 89 - - 88 - - 89 - dbc f i =30mhz -88- -88- -88- -88-dbc f i =70mhz -87- -87- -86- -86-dbc f i = 170 mhz - 84 - - 85 - - 83 - - 84 - dbc ? ct(ch) channel crosstalk f i = 70 mhz - 100 - - 100 - - 100 - - 100 - dbc table 7. dynamic characteristics [1] ?continued symbol parameter conditions adc1412d065 adc1412d080 adc1412d105 adc1412d125 unit min typ max min typ max min typ max min typ max table 8. clock and digital outp ut timing characteristics [1] symbol parameter conditions adc1412d065 adc1412d080 adc1412d105 adc1412d125 unit min typ max min typ max min typ max min typ max clock timing input: pins clkp and clkm f clk clock frequency 20 - 65 60 - 80 75 - 105 100 - 125 mhz t lat(data) data latency time -14- -14- -14- -14-clock cycles ? clk clock duty cycle dcs_en = 1 30 50 70 30 50 70 30 50 70 30 50 70 % dcs_en = 0 455055455055455055455055% t d(s) sampling delay time - 0.8 - - 0.8 - - 0.8 - - 0.8 - ns t wake wake-up time -76- -76- -76- -76- ? s cmos mode timing: pins da13 to da0, db13 to db0 and dav t pd propagation delay data - 3.9 - - 3.9 - - 3.9 - - 3.9 - ns dav -4.2- -4.2- -4.2- -4.2-ns t su set-up time - 8.6 - - 7.4 - - 6.1 - - 5.7 - ns t h hold time - 4.8 - - 3.4 - - 1.8 - - 1.4 - ns t r rise time data [2] 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns dav 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns t f fall time data [2] 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 12 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs [1] typical values measured at v dda =3v, v ddo =1.8v, t amb =25 ? c; minimum and maximum values are ac ross the full temperature range t amb = ? 40 ? cto +85 ? c at v dda =3v, v ddo = 1.8 v; v inap ? v inam = ? 1 dbfs; v inbp ? v inbm = ? 1 dbfs; unless otherwise specified. [2] measured between 20 % to 80 % of v ddo . [3] rise time measured from ? 50 mv to +50 mv; fall time measured from +50 mv to ? 50 mv. lvds ddr mode timing: pins da12_da13_p to da0_da1_p, da12_da1 3_m to da0_da1_m, db12_db13_p to db0_db1_p, db12_db13_m to db0_db1_m, davp and davm t pd propagation delay data - 3.9 - - 3.9 - - 3.9 - - 3.9 - ns dav -4.2- -4.2- -4.2- -4.2-ns t su set-up time - 5.1 - - 3.5 - - 2.1 - - 1.4 - ns t h hold time - 2.0 - - 2.0 - - 2.0 - - 2.0 - ns t r rise time data [3] 50 100 200 50 100 200 50 100 200 50 100 200 ps dav 50 100 200 50 100 200 50 100 200 50 100 200 ps t f fall time data [3] 50 100 200 50 100 200 50 100 200 50 100 200 ps dav 50 100 200 50 100 200 50 100 200 50 100 200 ps table 8. clock and digital outp ut timing characteristics [1] ?continued symbol parameter conditions adc1412d065 adc1412d080 adc1412d105 adc1412d125 unit min typ max min typ max min typ max min typ max
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 13 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs t clk =1/f clk fig 4. cmos mode timing t clk =1/f clk fig 5. lvds ddr mode timing (n ? 12) t d(s) t clk n n + 1 n + 2 t clk t su t pd t h t pd clkp clkm data dav 005aaa060 (n ? 11) (n ? 13) (n ? 14) 005aaa114 (n ? 14) t d(s) t clk n n + 1 n + 2 clkp clkm davp davm t pd (n ? 11) (n ? 12) (n ? 13) da x / db x da x / db x da x / db x da x / db x da x+1/ db x+1 da x+1/ db x+1 da x+1/ db x+1 da x+1/ db x+1 da x+1/ db x+1 da x _ da x + 1 _ p/ db x _ db x + 1 _ p da x _ da x + 1 _ m/ db x _ db x + 1 _ m da x / db x t pd t clk t h t su t h t su
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 14 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 10.3 spi timings [1] typical values measured at v dda =3v, v ddo = 1.8 v, t amb =25 ? c; minimum and maximum values are across the full temperature range t amb = ? 40 ? c to +85 ? c at v dda =3v, v ddo =1.8v. table 9. characteristics symbol parameter conditions min typ max unit spi timings t w(sclk) sclk pulse width - 40 - ns t w(sclkh) sclk high pulse width - 16 - ns t w(sclkl) sclk low pulse width - 16 - ns t su set-up time data to sclk high - 5 - ns cs to sclk high - 5 - ns t h hold time data to sclk high - 2 - ns cs to sclk high - 2 - ns f clk(max) maximum clock frequency - 25 - mhz fig 6. spi timing t su sdio sclk r/w w1 w0 a12 a11 d2 d1 d0 t su t h t h t w(sclk) 005aaa065 cs t w(sclkl) t w(sclkh)
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 15 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 10.4 typical characteristics fig 7. capacitance as a function of frequency fig 8. resistance as a function of frequency f (mhz) 50 550 450 250 350 150 001aam619 2.8 2.6 3.0 3.2 c (pf) 2.4 f (mhz) 50 550 450 250 350 150 001aam614 8 4 12 16 r (k ) 0 t=25 ? c; v dd =3v; f i = 170 mhz; f s = 125 msps (1) dcs on (2) dcs off t=25 ? c; v dd =3v; f i = 170 mhz; f s = 125 msps (1) dcs on (2) dcs off fig 9. sfdr as a function of duty cycle ( ? ) fig 10. snr as a function of duty cycle ( ? ) (%) 10 90 70 30 50 001aam616 40 60 20 80 100 sfdr (dbc) 0 (1) (2) (%) 10 90 70 30 50 001aam615 40 20 60 80 snr (dbfs) 0 (1) (2)
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 16 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs (1) t amb = ? 40 ? c/typical supply voltages (2) t amb =+25 ? c/typical supply voltages (3) t amb =+90 ? c/typical supply voltages (1) t amb = ? 40 ? c/typical supply voltages (2) t amb =+25 ? c/typical supply voltages (3) t amb =+90 ? c/typical supply voltages fig 11. sfdr as a function of duty cycle ( ? ) fig 12. snr as a function of duty cycle ( ? ) (%) 10 90 70 30 50 001aam617 84 88 92 sfdr (dbc) 80 (1) (2) (3) (%) 10 90 70 30 50 001aam618 40 60 80 snr (dbfs) 20 (1) (2) (3) fig 13. sfdr as a function of common-mode input voltage (v i(cm) ) fig 14. snr as a function of common-mode input voltage (v i(cm) ) v i(cm) (v) 3.5 2.5 0.5 3.0 2.0 1.0 0 1.5 001aam659 78 74 86 82 90 sfdr (dbc) 70 v i(cm) (v) 3.5 2.5 0.5 3.0 2.0 1.0 0 1.5 001aam660 69 67 73 71 75 snr (dbfs) 65
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 17 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 11. application information 11.1 device control the adc1412d can be controlled via the serial peripheral interface (spi control mode) or directly via the i/o pins (pin control mode). 11.1.1 spi and pin control modes the device enters pin control mode at power-up and remains in this mode as long as pin cs is held high. in pin control mode, the spi pins sdio, cs and sclk are used as static control pins. spi control mode is enabled by forcing pin cs low. once spi control mode has been enabled, the device remains in this mode. th e transition from pin control mode to spi control mode is illustrated in figure 15. when the device enters spi control mode, the output data standard and data format are determined by the level on pin sdio as soon as a transition is triggered by a falling edge on cs . 11.1.2 operating mode selection the active adc1412d operating mode (power-up, power-down or sleep) can be selected via the spi interface (see table 21) or by using pin ctrl in pin control mode, as described in table 10. 11.1.3 selecting the output data standard the output data standard (cmos or lvds ddr) can be selected via the spi interface (see table 24) or by using pin ods in pin control mode. lvds ddr is selected when ods is high, otherwise cmos is selected. fig 15. control mode selection r/w spi control mode pin control mode data format offset binary data format two's complement lvds ddr sdio/ods sclk/dfs w1 w0 a12 005aaa039 cmos cs table 10. operating mode selection via pin ctrl pin ctrl operating mode output high-z 0 power-down yes 0.3v dda sleep yes 0.6v dda power-up yes v dda power-up no
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 18 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 11.1.4 selecting the output data format the output data format can be selected via the spi interface (offset binary, two?s complement or gray code; see table 24) or by using pin dfs in pin control mode (offset binary or two?s complement). offset binary is selected when dfs is low. when dfs is high, two?s complement is selected. 11.2 analog inputs 11.2.1 input stage the analog input of the adc1412d supports a di fferential or a single-ended input drive. optimal performance is achieved using diff erential inputs with the common-mode input voltage (v i(cm) ) on pins inap, inam, inbp and inbm set to 0.5v dda . the full-scale analog input voltage range is configurable between 1 v (p-p) and 2 v (p-p) via a programmable internal reference (see section 11.3 and table 23). the equivalent circuit of the sample-and-h old input stage, including electrostatic discharge (esd) protection and circuit and package parasitics, is shown in figure 16. the sample phase occurs when the internal clock (derived from the clock signal on pin clkp/clkm) is high. the voltage is then he ld on the sampling capacitors. when the clock signal goes low, the stage enters the hold phase and the voltage information is transmitted to the adc core. 11.2.2 anti-kickback circuitry anti-kickback circuitry (rc filter in figure 17 ) is needed to counteract the effects of charge injection generated by the sampling capacitance. the rc filter is also used to filter noise from the signal before it reaches the sampling stage. the value of the capacitor should be ch osen to maximize noise attenuation without degrading the settling time excessively. fig 16. input sampling circuit 005aaa092 inap/inbp package esd parasitics switch r on = 14 4 pf 4 pf sampling capacitor sampling capacitor switch r on = 14 inam/inbm internal clock internal clock
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 19 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs the component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. 11.2.3 transformer the configuration of the transf ormer circuit is determined by the input frequency. the configuration shown in figure 18 would be suitable for a baseband application. the configuration shown in figure 19 is recomme nded for high frequency applications. in both cases, the choice of transformer is a compromise between cost and performance. fig 17. anti-kickback circuit table 11. rc coupling versus input frequency, typical values input frequency (mhz) r ( ? ) c (pf) 32512 70 12 8 170 12 8 001aan679 r r c inap/ inbp inam/ inbm fig 18. single transformer configuratio n suitable for baseband applications 005aaa094 100 nf 100 nf 100 nf 100 nf 25 25 25 25 12 pf inap/inbp inam/inbm vcma/vcmb 100 nf analog input adt1-1wt 100 nf
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 20 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 11.3 system reference and power management 11.3.1 internal/external references the adc1412d has a stable and accurate built-in internal reference voltage to adjust the adc full-scale. this reference voltage can be se t internally via spi or with pins vref and sense (programmable in 1 db steps between 0 db and ? 6 db via control bits intref[2:0] when bit intref_en = logic 1; see table 23). see figure 21 to figure 24. the equivalent reference circuit is shown in figure 20. external reference is also possible by providing a voltage on pin vref as described in figure 23. fig 19. dual transformer configuration suitable for high intermediate frequency application 005aaa095 100 nf 100 nf 100 nf 100 nf 12 12 8.2 pf inap/inbp inam/inbm vcma/vcmb 50 50 50 50 adt1-1wt adt1-1wt analog input
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 21 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs if bit intref_en is set to logic 0, the reference voltage is determined either internally or externally as detailed in table 12. [1] the voltage on pin vref is doubled internally to generate the internal reference voltage. fig 20. reference equivalent schematic table 12. reference selection selection spi bit intref_en sense pin vref pin full-scale (v (p-p)) internal (figure 21) 0 agnd 330 pf capacitor to agnd 2 v internal (figure 22) 0 pin vref connected to pin sense and via a 330 pf capacitor to agnd 1 v external (figure 23) 0v dda external voltage between 0.5v and 1v [1] 1 v to 2 v internal via spi (figure 24) 1 pin vref connected to pin sense and via 330 pf capacitor to agnd 1 v to 2 v ext_ref ext_ref 001aan670 refat/ refbt refab/ refbb sense vref selection logic bandgap reference adc core buffer reference amp
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 22 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs figure 21 to figure 24 illustrate how to connect the sense and vref pins to select the required reference voltage source. 11.3.2 programmable full-scale the full-scale is programmable between 1 v (p-p) to 2 v (p-p) (see table 13). 11.3.3 common-mode output voltage (v o(cm) ) a 0.1 ? f filter capacitor should be connected between pin vcma/vcmb and ground to ensure a low-noise common-mode output voltage. when ac-coupled, pin vcma/vcmb can then be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point. fig 21. internal reference, 2 v (p-p) full scale fig 22. internal reference, 1 v (p-p) full scale fig 23. external reference, 1 v (p-p) to 2 v (p-p) full-scale fig 24. internal reference vi a spi, 1 v (p-p) to 2 v (p-p) full-scale 330 pf vref sense 005aaa116 reference equivalent schematic 330 pf 005aaa117 vref sense reference equivalent schematic 0.1 f vdda v 005aaa119 vref sense reference equivalent schematic reference equivalent schematic 330 pf 005aaa118 vref sense table 13. programmable full-scale intref level (db) full-scale (v (p-p)) 000 0 2 001 ? 11.78 010 ? 21.59 011 ? 31.42 100 ? 41.26 101 ? 51.12 110 ? 61 111 reserved x
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 23 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 11.3.4 biasing the common-mode input voltage (v i(cm) ) on pins inap/inbp and inam/inbm should be set externally to 0.5v dda for optimal performance and should always be between 0.9 v and 2 v (see table 6). 11.4 clock input 11.4.1 drive modes the adc1412d can be driven differentially (lvpecl). it can also be driven by a single-ended lvcmos signal connected to pin clkp (pin clkm should be connected to ground via a capacitor) or pin clkm (pin clkp should be connected to ground via a capacitor). fig 25. equivalent schematic of the common-mode reference circuit 1.5 v vcma/vcmb 0.1 f package esd parasitics 005aaa099 common mode reference adc core a. rising edge lvcmos b. falling edge lvcmos fig 26. lvcmos single-ended clock input lvcmos clock input clkp clkm 005aaa174 005aaa053 lvcmos clock input clkp clkm
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 24 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs a. sine clock input b. sine clock input (with transformer) c. lvds clock input d. lvpecl clock input fig 27. differential clock input sine clock input clkp clkm 005aaa173 sine clock input clkp clkm 005aaa054 005aaa055 lvds clock input clkp clkm lvpecl clock input 005aaa172 clkp clkm
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 25 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 11.4.2 equivalent input circuit the equivalent circuit of the input clock buf fer is shown in figure 28. the common-mode voltage of the differential input stage is set via internal 5 k ? resistors. single-ended or differential clock inputs c an be selected via the spi interface (see table 22). if single-ended is enabled, the input pin (clkm or clkp) is selected via control bit se_sel. if single-ended is implemented without settin g bit se_sel to the appropriate value, the unused pin should be connected to ground via a capacitor. 11.4.3 duty cycle stabilizer the duty cycle stabilizer can improve th e overall performance of the adc by compensating the duty cycle of the input clock signal. when the duty cycle stabilizer is active (bit dcs_en = logic 1; see table 22), th e circuit can handle signals with duty cycles of between 30 % and 70 % (typical). when the duty cycle stabilizer is disabled (dcs_en = logic 0), the input clock signal s hould have a duty cycle of between 45 % and 55 %. 11.4.4 clock input divider the adc1412d contains an input clock divider that divides the incoming clock by a factor of 2 (when bit clkdiv = logic 1; see table 22). this feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better snr result once acquisition has been performed. v cm(clk) = common-mode voltage of the differential input stage fig 28. equivalent input circuit clkp clkm 005aaa056 package esd parasitics 5 k 5 k v cm(clk) se_sel se_sel
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 26 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 11.5 digital outputs 11.5.1 digital output buffers: cmos mode the digital output buffers can be configured as cmos by setting bit lvds_cmos to logic 0 (see table 24). each digital output has a dedicated output buffer. the equivalent circuit of the cmos digital output buffer is shown in figure 29. the buffer is powered by a separate agnd/v ddo to ensure 1.8 v to 3.3 v compatibility and is isolated from the adc core. each buffer can be loaded by a maximum of 10 pf. the output resistance is 50 ? and is the combination of an internal resistor and the equivalent output resistance of the buffer. there is no need for an external damping resistor. the drive strength of both data and dav buffers can be programmed via the spi in order to adjust the rise and fall times of the output digital signals (see table 31). fig 29. cmos digital output buffer vddo esd package parasitics agnd dx 005aaa057 50 logic driver
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 27 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 11.5.2 digital output buffers: lvds ddr mode the digital output buffers can be configured as lvds ddr by setting bit lvds_cmos to logic 1 (see table 24). each output should be terminated externally with a 100 ? resistor (typical) at the receiver side (figure 30) or internally via spi control bits lvds_int_ter[2:0] (see figure 31 and table 33). the default lvds ddr output bu ffer current is set to 3.5 m a. it can be programmed via the spi (bits davi[1:0] and datai[1:0]; see table 32) in order to adjust the output logic voltage levels. fig 30. lvds ddr digital output buffer - externally terminated fig 31. lvds ddr digital output buffer - internally terminated dan_dan + 1_m; dbn_dbn + 1_m vddo 3.5 ma typical agnd 100 - 005aaa112 + - + receiver dan_dan + 1_p; dbn_dbn + 1_p dan_dan + 1_p; dbn_dbn + 1_p dan_dan + 1_m; dbn_dbn + 1_m vddo 3.5 ma typical agnd 100 - 005aaa113 + - + receiver 100
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 28 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 11.5.3 data valid (dav) output clock a data valid (dav) output clock signal is provided that can be used to capture the data delivered by the adc1412d. detailed timing diagrams for cmos and lvds ddr modes are provided in figure 4 and figure 5 respecti vely. in lvds ddr mode, it is highly recommended to shift ahead the dav by 1 ns (bits davphase[2:0] = 0b100; see table 25). 11.5.4 out-of-range (otr) an out-of-range signal is provided on pin otra for adc channel a and on pin otrb for adc channel b. the latency of otra/b is fo urteen clock cycles. the otr response can be speeded up by enabling fast otr (bit fastotr = logic 1; see table 30). in this mode, the latency of otra/b is reduced to only four clock cycles (separately for each adc channel). the fast otr detection threshold (below full-scale) can be programmed via bits fastotr_det[2:0]. 11.5.5 digital offset by default, the adc1412d delivers output co de that corresponds to the analog input. however, it is possible to add a digital offset to the output code via the spi (bits dig_offset[5:0]; see table 26). table 14. lvds ddr output register 2 lvds_int_ter[2:0] resistor value ( ? ) 000 no internal termination 001 300 010 180 011 110 100 150 101 10 110 81 111 60 table 15. fast otr register fastotr_det[2:0] detection level (db) 000 ? 20.56 001 ? 16.12 010 ? 11.02 011 ? 7.82 100 ? 5.49 101 ? 3.66 110 ? 2.14 111 ? 0.86
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 29 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 11.5.6 test patterns for test purposes, the adc1412d can be configured to transmit one of a number of predefined test patterns (via bits testpat_ sel[2:0]; see table 27). a custom test pattern can be defined by the user (testpat_user[13:6]; see table 28 and testpat_user[5:0]; see table 29) and is selected when testpat_sel[2:0] = 101. the selected test pattern is transmitted regardless of the analog input. 11.5.7 output codes versus input voltage 11.6 serial peripheral interface (spi) 11.6.1 register description the adc1412d serial interface is a synchronous serial communicatio ns port that allows easy interfacing with many commonly used mi croprocessors. it provides access to the registers that control the operation of the chip. this interface is configured as a 3- wire type (sdio as bidirectional pin). pin sclk is the serial clock input and cs is the chip select pin. each read/write operation is initiated by a low level on cs . a minimum of three bytes is transmitted (two instruction bytes and at least one data byte). the number of data bytes is determined by the value of bits w1 and w2 (see table 18). table 16. output codes v inap ? v inam / v inbp ? v inbm offset binary two?s complement otra/otrb pin < ? 1 00 0000 0000 0000 10 0000 0000 0000 1 ? 1 00 0000 0000 0000 10 0000 0000 0000 0 ? 0.9998779 00 0000 0000 0001 10 0000 0000 0001 0 ? 0.9997559 00 0000 0000 0010 10 0000 0000 0010 0 ? 0.9996338 00 0000 0000 0011 10 0000 0000 0011 0 ? 0.9995117 00 0000 0000 0100 10 0000 0000 0100 0 .... .... .... 0 ? 0.0002441 01 1111 1111 1110 11 1111 1111 1110 0 ? 0.0001221 01 1111 1111 1111 11 1111 1111 1111 0 +0 10 0000 0000 0000 00 0000 0000 0000 0 +0.0001221 10 0000 0000 0001 00 0000 0000 0001 0 +0.0002441 10 0000 0000 0010 00 0000 0000 0010 0 .... .... .... 0 +0.9995117 11 1111 1111 1011 01 1111 1111 1011 0 +0.9996338 11 1111 1111 1100 01 1111 1111 1100 0 +0.9997559 11 1111 1111 1101 01 1111 1111 1101 0 +0.9998779 11 1111 1111 1110 01 1111 1111 1110 0 +1 11 1111 1111 1111 01 1111 1111 1111 0 > +1 11 1111 1111 1111 01 1111 1111 1111 1
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 30 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs [1] bit r/w indicates whether it is a read (1) or a write (0) operation. [2] bits w1 and w0 indicate the number of bytes to be transferred (see table 18). bits a12 to a0 indicate the address of the register being accessed. in the case of a multiple byte transfer, this address is the first register to be accessed. an address counter is increased to access subsequent addresses. the steps for a data transfer: 1. a falling edge on pin cs in combination with a rising edge on pin sclk determine the start of communications. 2. the first phase is the transfer of the 2-byte instruction. 3. the second phase is the transfer of the data which can vary in length but is always a multiple of 8 bits. the msb is always sent first (for instruction and data bytes). 4. a rising edge on pin cs indicates the end of data transmission. 11.6.2 default modes at start-up during circuit initialization it does not matter which output data standard has been selected. at power-up, the dev ice enters pin control mode. a falling edge on pin cs triggers a transition to spi control mode. when the adc1412d enters spi control mo de, the output data standard (cmo s/lvds ddr) is determined by the level on pin sdio (see figure 33). once in spi control mode, the output data standard can be changed via bit lvds_cmos (see ta b l e 2 4 ). table 17. instruction bytes for the spi msb lsb bit 76543210 description r/w [1] w1 [2] w0 [2] a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 table 18. number of data bytes to be transferred after the instruction bytes w1 w0 number of bytes transmitted 001 byte 012 bytes 103 bytes 1 1 4 bytes or more fig 32. spi mode timing cs sclk sdio r/w w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d3 d2 d1 d0 d0 d7 d6 d5 d4 instruction bytes register n (data) register n + 1 (data) 005aaa086
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 31 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs when the adc1412d enters spi control mode, the output data format (two?s complement or offset binary) is determined by the level on pin sclk (gray code can only be selected via the spi). once in spi control mode, the output data format can be changed via bit data_format[1:0] (see table 24). fig 33. default mode at start-up: sclk low = offset binary; sdio high = lvds ddr fig 34. default mode at start-up: sclk high = two?s complement; sdio low = cmos cs sdio (cmos lvds ddr) sclk (data format) offset binary, lvds ddr default mode at start-up 005aaa063 sdio (cmos lvds ddr) sclk (data format) two's complement, cmos default mode at start-up 005aaa064 cs
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 32 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 11.6.3 register allocation map table 19. register allocation map address (hex) register name access bit definition default (bin) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0003 channel index r/w reserved[5:0] adcb adca 11111 1111 0005 reset and operating mode r/w sw_ rst reserved[2:0] - - op_mode[1:0] 0000 0000 0006 clock r/w - - - se_sel diff_se - clkdiv dcs_en 0000 0001 0008 internal reference r/w - - - - intref_en intref[2:0] 0000 0000 0011 output data standard r/w - - - lvds_cmos outbuf outbus_swap data_format[1:0] 0000 0000 0012 output clock r/w - - - - davinv davphase[2:0] 0000 1110 0013 offset r/w - - dig_offset[5:0] 0000 0000 0014 test pattern 1 r/w - - - - - testpat_sel[2:0] 0000 0000 0015 test pattern 2 r/w testpat_user[13:6] 0000 0000 0016 test pattern 3 r/w testpat_user[5:0] - - 0000 0000 0017 fast otr r/w - - - - fastotr fastotr_det[2:0] 0000 0000 0020 cmos output r/w - - - - dav_drv[1:0] data_drv[1:0] 0000 1110 0021 lvds ddr o/p 1 r/w - - reserved da vi[1:0] reserved datai[1:0] 0000 0000 0022 lvds ddr o/p 2 r/w - - - - bit_byte_wise lvds_int_ter[2:0] 0000 0000
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 33 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs table 20. channel index control register (address 0003h) bit description default values are highlighted. bit symbol access value description 7 to 2 reserved[5:0] - 111111 reserved 1 adcb r/w next spi command for adc b 0 adc b not selected 1 adc b selected 0 adca r/w next spi command for adc a 0 adc a not selected 1 adc a selected table 21. reset and operating mode control register (address 0005h) bit description default values are highlighted. bit symbol access value description 7 sw_rst r/w reset digital section 0 no reset 1 performs a reset on spi registers 6 to 4 reserved[2:0] - 000 reserved 3 to 2 - - 00 not used 1 to 0 op_mode[1:0] r/w operating mode 00 normal (power-up) 01 power-down 10 sleep 11 normal (power-up) table 22. clock control register (address 0006h) bit description default values are highlighted. bit symbol access value description 7 to 5 - - 000 not used 4 se_sel r/w single-ended clock input pin select 0clkm 1clkp 3 diff_se r/w differential/single-ended clock input select 0 fully differential 1 single-ended 2 reserved - 0 reserved 1 clkdiv r/w clock input divide by 2 0 disabled 1 enabled 0 dcs_en r/w duty cycle stabilizer 0 disabled 1 enabled
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 34 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs table 23. internal reference control register (address 0008h) bit description default values are highlighted. bit symbol access value description 7 to 4 - - 0000 not used 3 intref_en r/w programmable internal reference enable 0 disable 1 active 2 to 0 intref[2:0] r/w programmable internal reference 000 0db (fs=2v) 001 ? 1 db (fs = 1.78 v) 010 ? 2 db (fs = 1.59 v) 011 ? 3 db (fs = 1.42 v) 100 ? 4 db (fs = 1.26 v) 101 ? 5 db (fs = 1.12 v) 110 ? 6db (fs=1v) 111 reserved table 24. output data standard control register (address 0011h) bit description default values are highlighted. bit symbol access value description 7 to 5 - - 000 not used 4 lvds_cmos r/w output data standard: lvds ddr or cmos 0cmos 1 lvds ddr 3 outbuf r/w output buffers enable 0 output enabled 1 output disabled (high z) 2 outbus_swap r/w output bus swap 0 no swapping 1 output bus is swapped (msb becomes lsb, vice versa) 1 to 0 data_format[1:0] r/w output data format 00 offset binary 01 two?s complement 10 gray code 11 offset binary
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 35 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs [1] t clk =1/f clk table 25. output clock register (address 0012h) bit description default values are highlighted. bit symbol access value description 7 to 4 - - 0000 not used 3 davinv r/w output clock data valid (dav) polarity 0 normal 1 inverted 2 to 0 davphase[2:0] r/w dav phase select 000 output clock shifted (ahead) by 6/16 ? t clk [1] 001 output clock shifted (ahead) by 5/16 ? t clk [1] 010 output clock shifted (ahead) by 4/16 ? t clk [1] 011 output clock shifted (ahead) by 3/16 ? t clk [1] 100 output clock shifted (ahead) by 2/16 ? t clk [1] 101 output clock shifted (ahead) by 1/16 ? t clk [1] 110 default value as defined in timing section 111 output clock shifted (delayed) by 1/16 ? t clk [1] table 26. offset register (add ress 0013h) bit description default values are highlighted. bit symbol access value description 7 to 6 - - 00 not used 5 to 0 dig_offset[5:0] r/w digital offset adjustment 011111 +31 lsb ... ... 000000 0 ... ... 100000 ? 32 lsb table 27. test pattern 1 register (address 0014h) bit description default values are highlighted. bit symbol access value description 7 to 3 - - 00000 not used 2 to 0 testpat_sel[2:0] r/w digital test pattern select 000 off 001 mid scale 010 ? fs 011 +fs 100 toggle ?1111..1111?/?0000..0 000? 101 custom test pattern 110 ?0101..0101? 111 ?1010..1010.?
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 36 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs table 28. test pattern 2 register (address 0015h) bit description default values are highlighted. bit symbol access value description 7 to 0 testpat_user[13:6] r/w 0000 0000 custom digital test pattern (bits 13 to 6) table 29. test pattern 3 register (address 0016h) bit description default values are highlighted. bit symbol access value description 7 to 2 testpat_user[5:0] r/w 000000 custom digital test pattern (bits 5 to 0) 1 to 0 - - 00 not used table 30. fast otr register (address 0017h) bit description default values are highlighted. bit symbol access value description 7 to 4 - - 0000 not used 3 fastotr r/w fast out-of-range (otr) detection 0 disabled 1 enabled 2 to 0 fastotr_det[2:0] r/w se t fast otr detection level 000 ? 20.56 db 001 ? 16.12 db 010 ? 11.02 db 011 ? 7.82 db 100 ? 5.49 db 101 ? 3.66 db 110 ? 2.14 db 111 ? 0.86 db table 31. cmos output register (address 0020h) bit description default values are highlighted. bit symbol access value description 7 to 4 - - 0000 not used 3 to 2 dav_drv[1:0] r/w drive strength for dav cmos output buffer 00 low 01 medium 10 high 11 very high 1 to 0 data_drv[1:0] r/w drive strength for data cmos output buffer 00 low 01 medium 10 high 11 very high
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 37 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs table 32. lvds ddr 1 output register (address 0021h) bit description default values are highlighted. bit symbol access value description 7 to 6 - - 00 not used 5 reserved - 0 reserved 4 to 3 davi[1:0] r/w lvds current for dav lvds buffer 00 3.5 ma 01 4.5 ma 10 1.25 ma 11 2.5 ma 2 reserved - 0 reserved 1 to 0 datai[1:0] r/w lvds current for data lvds buffer 00 3.5 ma 01 4.5 ma 10 1.25 ma 11 2.5 ma table 33. lvds ddr 2 output register (address 0022h) bit description default values are highlighted. bit symbol access value description 7 to 4 - - 0000 not used 3 bit_byte_wise r/w ddr mode for lvds output 0 bit wise (even data bits output on dav rising edge/odd data bits output on dav falling edge) 1 byte wise (msb data bits output on dav rising edge/lsb data bits output on dav falling edge) 2 to 0 lvds_int_ter[2:0] r/w internal termination for lvds buffer (dav and data) 000 no internal termination 001 300 ? 010 180 ? 011 110 ? 100 150 ? 101 100 ? 110 81 ? 111 60 ?
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 38 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 12. package outline fig 35. package outline sot804-3 (hvqfn64) references outline version european projection issue date iec jedec jeita sot804-3 - - - - - - - - - sot804-3_po unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.30 0.21 0.18 0.2 9.1 9.0 8.9 9.1 9.0 8.9 0.5 0.1 0.05 a dimensions note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 x 9 x 0.85 mm sot804-3 a 1 bcd (1) 0.1 y 1 d h 7.25 7.10 6.95 e (1) e h 7.25 7.10 6.95 ee 1 7.5 e 2 7.5 l 0.5 0.4 0.3 vw 0.05 y 0 2.5 5 mm scale terminal 1 index area terminal 1 index area b d a e b e 1 e a c b v c w 17 32 e 2 e 33 48 d h 49 64 e h l 1 16 c y c y 1 x detail x a 1 a c 1/2 e 1/2 e 09-02-24 10-08-06
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 39 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 13. abbreviations table 34. abbreviations acronym description adc analog-to-digital converter cmos complementary metal oxide semiconductor dav data valid dcs duty cycle stabilizer dfs data format select esd electrostatic discharge imd intermodulation distortion fs full-scale lsb least significant bit lvcmos low voltage complementary metal oxide semiconductor lvds ddr low voltage differential signalling double data rate lvpecl low-voltage positive emitter-coupled logic msb most significant bit otr out-of-range sfdr spurious-free dynamic range snr signal-to-noise ratio spi serial peripheral interface tx transmitter
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 40 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 14. revision history 15. contact information for more information or sales office addresses, please visit: http://www.idt.com table 35. revision history document id release date data sheet status change notice supersedes adc1412d_ser v.5 20120702 product data sheet - adc1412d_ser v.4 adc1412d_ser v.4 20110304 product data sheet - adc1412d_ser v.3 modifications: ? data sheet status changed from preliminary to product. ? text and drawings updated throughout entire data sheet. ? section 10.4 ?typical characteristics? has been added to the data sheet. ? section 13 ?abbreviations? has been added to the data sheet. adc1412d_ser v.3 20100806 preliminary data sheet - adc1412d065_080_105_125 v.2 adc1412d065_080_105_125 v.2 20090604 objective data sheet - adc1412d065_080_105_125 v.1 adc1412d065_080_105_125 v.1 20090528 objective data sheet - -
adc1412d_ser 5 ? idt 2012. all rights reserved. product data sheet rev. 05 ? 2 july 2012 41 of 41 integrated device technology adc1412d series dual 14-bit adc: cmos or lvds ddr digital outputs 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 cmos outputs selected . . . . . . . . . . . . . . . . . . 3 6.1.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 lvds ddr outputs selected. . . . . . . . . . . . . . . 5 6.2.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 thermal characteristics . . . . . . . . . . . . . . . . . . 7 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 7 10 dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.1 dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.2 clock and digital output timing . . . . . . . . . . . . 11 10.3 spi timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 10.4 typical characteristics . . . . . . . . . . . . . . . . . . 15 11 application information. . . . . . . . . . . . . . . . . . 17 11.1 device control . . . . . . . . . . . . . . . . . . . . . . . . . 17 11.1.1 spi and pin control modes . . . . . . . . . . . . . . . 17 11.1.2 operating mode selection. . . . . . . . . . . . . . . . 17 11.1.3 selecting the output data standard . . . . . . . . . 17 11.1.4 selecting the output data format. . . . . . . . . . . 18 11.2 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 18 11.2.1 input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11.2.2 anti-kickback circuitry . . . . . . . . . . . . . . . . . . 18 11.2.3 transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11.3 system reference and power management . . 20 11.3.1 internal/external references . . . . . . . . . . . . . . 20 11.3.2 programmable full-scale . . . . . . . . . . . . . . . . 22 11.3.3 common-mode output voltage (v o(cm) ) . . . . . 22 11.3.4 biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11.4 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11.4.1 drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 23 11.4.2 equivalent input circuit . . . . . . . . . . . . . . . . . . 25 11.4.3 duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 25 11.4.4 clock input divider . . . . . . . . . . . . . . . . . . . . . 25 11.5 digital outputs . . . . . . . . . . . . . . . . . . . . . . . . 26 11.5.1 digital output buffers: cmos mode . . . . . . . . 26 11.5.2 digital output buffers: lvds ddr mode . . . . 27 11.5.3 data valid (dav) output clock . . . . . . . . . . . . 28 11.5.4 out-of-range (otr) . . . . . . . . . . . . . . . . . . . 28 11.5.5 digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.5.6 test patterns . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.5.7 output codes versus input voltage. . . . . . . . . 29 11.6 serial peripheral interface (spi) . . . . . . . . . . 29 11.6.1 register description . . . . . . . . . . . . . . . . . . . . 29 11.6.2 default modes at start-up. . . . . . . . . . . . . . . . 30 11.6.3 register allocation map . . . . . . . . . . . . . . . . . 32 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 38 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 39 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 40 15 contact information . . . . . . . . . . . . . . . . . . . . 40 16 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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